The manufacture of integrated electronic circuits, being passive or active components, from semiconductor or insulating wafers, is generally performed in circuit batches, which may or may not be identical, on the same wafer. Once the circuits have been manufactured, they are generally tested, for example, by means of a probe testing board, to detect possible defective circuits. Such defective circuits are then identified so as not to be selected from the wafer after sawing by the pick-and-place equipment.
FIG. 1 shows very schematically in block form an example of a system for manufacturing integrated circuits IC from wafers P, for example, semiconductor wafers.
Generally, the process of manufacturing integrated circuits in batches on a same wafer P is performed in a first manufacturing location 1 (symbolized by a block FE, “Front End”) in which the integrated circuits are formed on the wafers and are tested.
A first known method of identifying possibly defective circuits consists of depositing an ink drop (inking) on these circuits to enable their subsequent recognition by optical devices associated with the pick-and-place equipment.
A second known technique to which embodiments of the present invention apply consists of recording a file containing the coordinates (generally rectangular) of the defective (or conversely, valid) circuits in the wafer to enable subsequent tracking thereof.
In such a case, the file containing the coordinates of the good and/or bad wafers is transmitted, simultaneously with wafers P, to another manufacturing location (BE or “Back End”) symbolized by a block 2, in which the wafers are sawed (block 3, SAWING) after usually having been placed on an adhesive support disk or film. Sawed wafers P resulting from this step are then processed by a pick-and-place equipment (not shown) provided with elements (block 4, SEL) for selecting the correct integrated circuits IC from a mapping (block 5, MAP) derived from the transmitted coordinate file. The mappings of the different tested wafers are stored with an identifier of the wafer, in the form of digital files at the wafer manufacturing site and at the assembly site, by for example transferring them through a central server (not shown).
FIGS. 2 and 3 respectively illustrate, by means of a schematic plan view of an integrated circuit wafer P and a table T of coordinates of defective or valid circuits, the operation of a pick-and-place circuit of the type to which embodiments of the present invention apply. Coordinates X and Y of the different integrated circuits IC stored in table T correspond either to the valid integrated circuits IC of FIG. 2, or to defective integrated circuits DIC illustrated in FIG. 2 with crosses. Visually, such defective circuits are not differentiated from correct circuits since embodiments of the present invention relate to an inkless circuit.
To enable initial alignment of the pick-and-place equipment with respect to the wafer, a reference chip (R, FIG. 2), for which the pick-and-place equipment will search based on the file coordinates, is generally selected, allowing subsequent processing of the coordinates contained in the file associated with the wafer. This reference chip enables the validation of an origin position of the mapping in the reference frame of the equipment.
For example, an approximate calculation of the wafer center is exploited to align the equipment (more specifically its visual or optical sensor) on reference chip R based on the coordinates read from a file. Then, a location in the chip (often a corner) to which the coordinates correspond is searched by successive iterations. Once the position of the reference chip is known in the reference frame of the equipment, the rest of the file becomes, in principle, interpretable. The valid chips are then picked from the adhesive support disk, generally by a line scanning of the wafer chips, the defective chips being left on the disk.
Known methods and systems of this type are described, for example, in U.S. Pat. Nos. 6,380,000 and 6,756,796.
Such a solution is acceptable for chips of relatively large dimensions but becomes unsatisfactory as the chip size decreases. Indeed, the wafer sawing generally generates an expansion due the flexibility of the film then supporting the different chips. This expansion added to the alignment tolerances generates a risk that the approximate alignment will select an erroneous reference chip (the chip neighboring the reference chip). In the case of an error of this type, the use of the coordinate file becomes incorrect.
Using two reference chips at two different locations of the wafer to correct possible positioning tolerances has been proposed.
A disadvantage of such a solution is that if the pick-and-place equipment stops (for example, accidentally), upon restarting it is impossible to recover the reference if one of these reference chips has been picked for assembly.
It could have been envisioned to record the coordinates of the reference chips but to leave them on the support film and not to pick them for assembly. A disadvantage is then that two chips per wafer are lost if the chips present at the reference positions are correct. Further, picking these chips last adversely affects the efficiency of the equipment by requiring a reverse during scanning. Further, this does not solve the problem for the case where several chips of different sizes and destinations are supported by a same wafer.
DE-A-10219346 and JP-A-63136542 disclose processes wherein chips are marked after manufacturing.
EP-A-1424723 discloses a chip marking method by geometrical patterns made during manufacturing that necessitates a post-manufacturing step for having the patterns optically recognizable.